As the dimensions of transistors decrease, the thickness of the gate oxide must be reduced to maintain performance with the decreased gate length. However, in order to reduce gate leakage, high dielectric constant (high-k) gate oxide layers are used which allow greater physical thicknesses while maintaining the same effective thickness as would be provided by a typical gate oxide used in future technology nodes.
Additionally, as technology nodes shrink, in some integrated circuit (IC) designs, there has been a desire to replace the typically polysilicon gate electrode with a metal gate electrode to improve device performance with the decreased feature sizes. One process of forming the metal gate electrode is termed “gate last” process in which the final metal gate electrode is fabricated “last” which allows for reduced number of subsequent processes, including high temperature processing, that must be performed after formation of the gate.
FIGS. 1A-C show cross-sectional views of a plurality of conventional gate structures 101 for semiconductor devices 100 at various stages of fabrication in a “gate last” process. FIG. 1A illustrates the plurality of gate structures 101 may be formed by sequentially depositing and patterning a dummy oxide layer 106 and a dummy gate electrode layer (not shown) on the silicon substrate 102 including isolation regions 104; forming lightly doped source/drain (LDD) regions 112 in the substrate 102; surrounding the dummy oxide layer 106 and the dummy gate electrode layer with a nitrogen-containing dielectric layer 110; forming source/drain (S/D) regions 114 in the substrate 102; surrounding the nitrogen-containing dielectric layer 110 with a contact etch stop layer 116 and an interlayer dielectric (ILD) layer 118, such as silicon oxide; removing the dummy gate electrode layer to form an opening 120 in the nitrogen-containing dielectric layer 110.
However, problems arise when subsequently removing the dummy oxide layer 106 to form a larger opening 130 in the nitrogen-containing dielectric layer 110, which typically involve wet and/or dry etching steps. During wet etching step, top portions of the ILD layer 118 are isotropically removed leaving a plurality of recesses 118a in the ILD layer 118 (shown in FIG. 1B). This is due to the use of hydrofluoric (HF) acid in the wet etching steps, and the opening 120 limits entrance of the HF acid into interior surface of the opening 120. Thus, less HF acid reaches bottom of the opening 120, i.e., top of the dummy oxide layer 106, so more of the ILD layer 118 reacts and less removed from the dummy oxide layer 106. In another way, FIG. 1C shows a plurality of recesses 102a in the silicon substrate 102 may be formed due to the use of plasma during dry etching step, which recesses the silicon substrate 102. The plurality of recesses 102a or 118a are problematic in various respects. For example, the plurality of recesses 102a present in the silicon substrate 102 may change dopants distribution in channel regions. Thus, performance characteristics such as threshold voltage and reliability may degrade. For another example, the plurality of recesses 118a present in the ILD layer 118 can become a receptacle of metals during subsequent processing thereby increasing the likelihood of electrical shorting and/or device failure.
Accordingly, what is needed is a method for fabricating a gate structure having almost no recess in the interlayer dielectric layer or the substrate.